Phase-locked loops (PLL's) are widely used for generating clocks for a variety of systems. More recently, analog PLL's have been replaced by digital PLLs. Digital controls in such digital PLLs' may be less susceptible to noise while consuming less power.
However, digital phase-lock systems have a quantization error that results in a finite phase error. This quantization error is not preset in analog systems. The finite phase error produced by the digital oscillator appears on the output clock. However, this finite phase error is amplified by the feedback divider and applied to the phase comparator. The loose phase tracking with the input clock ultimately results in increased jitter in the form of a large close-in phase noise.
FIG. 1 is a graph of estimated phase noise in a prior-art digital phase-lock system. Phase noise is plotted as a function of offset frequency from the center frequency of the oscillator, such as 2.4 GHz. FIG. 1 shows that the phase noise is high at low offset frequencies. However, this phase noise is much lower for large frequency offsets.
One solution to the close-in phase noise problem is to use a delta-sigma modulator (DSM) to control the least-significant-bit (LSB) of the digital value applied as the input to the digital-controlled oscillator (DCO). The DSM improvers the tuning of the feedback clock to improve the quantization error and reduce the finite phase error. The lower finite phase error that is amplified by the feedback divider results in a more accurate phase tracking in the front end, and thus reduces close-in phase noise.
FIG. 2 is a graph of estimated phase noise in a prior-art digital phase-lock system using a delta-sigma modulator (DSM). The DSM (solid line) produces a lower close-in phase error than the standard digital phase system graphed in FIG. 1 (dotted line), reducing the phase error by about 30 dB in this example.
However, the DSM produces a larger far-away phase error, as can be seen at the higher frequencies in FIG. 2. Phase noise is transferred from close-in to far-away by the DSM. Jitter may be too high when higher frequencies are used. The closer the DSM is operated to the frequency of the output clock, the greater the shift of phase noise from close-in to far-away frequency regions.
Another problem with the DSM is that the DSM is operated at a high frequency, and has high power consumption at these high frequencies. The high speed logic can put a stress on the logic systems when the DSM is integrated with logic systems, such as on a System-On-a-Chip (SOC).
What is desired is a digital phase-lock system that has improved phase tracking without transferring phase noise from close-in to far-away frequency regions. A control circuit to replace the delta-sigma modulator (DSM) is desired. A control circuit that has few circuits operating at a high frequency is desirable to reduce power consumption and circuit complexity. A control circuit that uses dithering to reduce spur noise is also desirable.